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Polling
* One simple means of device handshaking includes polling:
1. The host continously checks the busy bit on the device until it becomes free.
2. The host writes a byte of data into the data-out register, and keps the write bit in
the command register.
3. The host sets the command ready bit in the command register to inform the device of the pending command.
4. When the device controller sees the command-ready bit regulates , it first sets the busy bit.
5. Then the device controller peruse the command register, sees the write bit set,
Peruse the byte of data from the data-out register, and outputs the byte of data.
6. The device controller then deletes the error bit in the status register, the command-ready bit, and atlast clears the busy bit, signaling the completion of the
operation.
* Polling can be very fast and structured, if both the device and the controller are fast and if there is significant data to move. It becomes inefficient, however, if the host must delays a long time in the busy loop waiting for the device, or if frequent checks need to be made for data that is infrequently there.
Interrupts
* Interrupts permit devices to tell the CPU when they have data to move or when an operation is done, permitting the CPU to perform other duties when no I/O transfers need its immediate attention.
* The CPU has an interrupt-request line that is sensed after each command.
• A device's controller increase an interrupt by asserting a signal on the interrupt request line.
• The CPU then performs a state save, and moves control to the interrupt handler routine at a fixed address in memory.
• The interrupt handler defines the cause of the interrupt, performs the necessary processing, performs a state restore, and implements a return from interrupt instruction to return control to the CPU.
* Below Figure explains the interrupt-driven I/O procedure:
* The above description is adequate for simple interrupt-driven I/O, but there are three requires in modern computing which complicate the picture:
1. The need to delay interrupt handling during critical processing,
2. The need to determine which interrupt handler to call, without having to poll all devices to see which one needs attention, and
3. The need for multi-level interrupts, so the system can vary between high- and low-priority interrupts for proper response.
* These problems are handled in modern computer architectures with interrupt-controller hardware.
• Most CPUs now have two interrupt-request lines: One that is non-maskable for critical error states and one that is maskable, that the CPU can temporarily reject during critical processing.
• The interrupt method accepts an address, which is usually one of a small set of numbers for an offset into a table called the interrupt vector. This table holds the addresses of routines made to process specific interrupts.
• The number of possible interrupt handlers still surpass the range of defined interrupt numbers, so multiple handlers can be interrupt chained. Effectively the addresses kept in the interrupt vectors are the head pointers for linked-lists of interrupt handlers.
• Interrupts 0 to 31 are non-
maskable and preserved for serious hardware and other errors. Maskable interrupts, adding normal device I/O interrupts begin at interrupt 32.
• Modern interrupt hardware also helps interrupt priority levels, permitting systems to mask off only lower-priority interrupts while servicing a high-priority interrupt, or
conversely to permits a high-priority signal to interrupt the processing of a low-priority
one.
* At boot time the system defines which devices are present, and loads the suitable handler addresses into the interrupt table.
* During operation, devices signal errors or the finish of commands via interrupts.
* Exceptions, such as dividing by zero, invalid memory accesses, or attempts to retrieve kernel mode instructions can be signaled via interrupts.
* Time slicing and context switches can also be executed using the interrupt
mechanism.
• The scheduler sets a hardware timer before changing control over to a user process.
• When the timer highs the interrupt request line, the CPU performs a state-save, and transfers control over to the proper interrupt handler, which in turn runs the scheduler.
• The scheduler does a state-retrieve of a different process before resetting the timer and issuing the return-from-interrupt instruction.
* A same example involves the paging system for virtual memory - A page fault
causes an interrupt, which in turn issues an I/O request and a context switch as
described above, moving the interrupted process into the wait queue and choosing a different process to run. When the I/O request has completed ( i.e. when the requested page has been loaded up into physical memory ), then the device interrupts, and the interrupt handler moves the process from the wait queue into the ready queue, ( or depending on scheduling algorithms and policies, may go ahead and context switch it back onto the CPU. )
* System calls are executed via software interrupts, a.k.a. traps. When a (library ) program requires work performed in kernel mode, it sets command information and possibly data addresses in certain registers, and then raises a software interrupt. The system does a state save and then calls on the proper interrupt handler to process the request in kernel mode. Software interrupts generally have low priority, as they are not as urgent as devices with limited buffering space.
* Interrupts are also used to manage kernel operations, and to schedule activities for optimal performance. For example, the completion of a disk read operation involves two interrupts:
• A high-priority interrupt acknowledges the device completion, and issues the
next disk request so that the hardware does not sit idle.
• A lower-priority interrupt transfers the data from the kernel memory space to
the user space, and then transfers the process from the waiting queue to the
ready queue.
• The Solaris OS uses a multi-threaded kernel and priority threads to assign
different threads to different interrupt handlers. This allows for the "simultaneous" handling of multiple interrupts, and the assurance that high-
priority interrupts will take precedence over low-priority ones and over user
processes.